# Cloudlifter circuit workshop An eight-lesson 3D build-along. Audience: a learner with basic soldering and multimeter skills, supported for the first powered test by someone comfortable with audio electronics. Timings are teaching estimates, excluding sourcing, fabrication, rework and full bench measurements. Read research/RESEARCH.md before purchasing or powering anything. All virtual progress means reviewed course material, never physical certification. ## Understand the circuit — 6 min **Performance objective:** Trace the balanced signal and the separate phantom-power route. A tiny signal enters the JFET gates. Phantom power arrives from the other end. The Cloudlifter circuit makes those two paths work together. Two LSK389 packages contain four JFETs. Q1 holds the input pair and Q2 the cascode pair. The receiving preamp supplies DC through its phantom feed resistors, which also participate in the circuit’s output load. A cascode is not the same as two complete gain stages in cascade. **Demonstration and guided practice:** 1. Find the female microphone input and the male interface output in the model. 2. Select Q1, then Q2. Each package contains two JFET sections, one for each balanced branch. 3. Open Circuit to follow the gate, source and drain connections. Keep the audio route separate from the DC power explanation. **Check before proceeding:** Explain why the audio interface needs phantom power on even though the SM7B itself does not need it. **Teaching note:** This is a reconstruction of the published CL-1 teardown circuit. The build view illustrates assembly. Flow & simulation uses a documented device model; physical hardware remains unmeasured. **Retrieval question:** Where does the booster get its operating power? **Feedback:** The receiving interface supplies phantom power on both balanced output conductors. The audio is the difference between those conductors; the power is common to them. **Blender treatment:** workshop-hero; isolate Q1, Q2, XLR_IN, XLR_OUT. Show the placement from above, then rotate for joint inspection. ## Prepare the board and parts — 7 min **Performance objective:** Match the PCB, package and component grade before assembly. Start with the actual board. Find the footprints and separate an electrical value from a library name. The PCB is 27.305 × 19.050 mm in the reference file. All six resistors and two capacitors use 1206 footprints. Q1 and Q2 use an eight-lead SOIC footprint. The schematic and author’s parts list specify LSK389C, while the PCB value strings retain LSK389B. Those grades have different IDSS ranges. **Demonstration and guided practice:** 1. Open Parts and sort the six resistor values, two capacitors, and two LSK389C SOIC packages into labelled positions. 2. Use Top view to locate J2 on the input side and J3 on the output side. Find the pad-1 mark for each SOIC. 3. Prepare magnification, fine tweezers, temperature-controlled soldering equipment, suitable flux, cleaning materials, a multimeter and a protected P48 test setup. Check the exact purchased parts’ assembly limits. **Check before proceeding:** Identify both SOIC pad-1 positions and explain the B/C discrepancy before ordering components. **Teaching note:** Use the current datasheet for the exact ordered package. A TO-71 device is not a drop-in fit for this SOIC PCB. Do not fabricate from the teaching enclosure. **Retrieval question:** Which JFET grade follows the instantiated schematic and the teardown parts list? **Feedback:** Use the C-grade selection from the schematic and teardown list. The B-labelled library and PCB metadata are a source discrepancy, not evidence that all grades are interchangeable. **Blender treatment:** board-overview; isolate PCB. Show the placement from above, then rotate for joint inspection. ## Place the six resistors — 10 min **Performance objective:** Populate each resistor by reference and verify its circuit role. Work from reference designators. Tiny resistors are easy to exchange; a neat joint cannot fix the wrong value. R1 is 39 Ω. R2 and R5 are 22 Ω. R3 and R6 are 33 kΩ input returns. R4 is the 3 kΩ resistor across the balanced input. R3 uses a capacitor-named footprint in the source PCB; it is still a resistor. **Demonstration and guided practice:** 1. With the board disconnected, measure and sort R1 39 Ω; R2/R5 22 Ω; R3/R6 33 kΩ; and R4 3 kΩ. 2. Select each reference in the model to locate it. Tack one pad, seat the component flat, then complete the second connection using an appropriate process. 3. Inspect alignment and both joints. Verify values against the parts list. In-circuit resistance can include parallel paths, so record pre-installation readings too. **Check before proceeding:** Point to the input load resistor and distinguish it from the two input-to-ground resistors. **Teaching note:** The resistance shown by a simulator or labelled model is not a meter reading from your board. **Retrieval question:** Which component provides the 3 kΩ differential input load? **Feedback:** R4 bridges the two input conductors. R3 and R6 each return an input conductor to ground; they add another differential resistive path through their series combination. **Blender treatment:** resistors; isolate R1, R2, R3, R4, R5, R6. Show the placement from above, then rotate for joint inspection. ## Add the RF capacitors — 7 min **Performance objective:** Place the two RF shunts and explain what they do. These capacitors sit beside the input returns. They shunt high-frequency interference toward ground. C1 and C2 are 1.8 nF, nonpolar, 1206 PEN film parts in the documented build. C1 connects input pin 2 to ground; C2 connects input pin 3 to ground. They are not series audio-coupling capacitors. The absence of a phantom feed to the microphone input comes from the circuit architecture, not from these capacitors blocking the line. **Demonstration and guided practice:** 1. Confirm 1.8 nF for both parts and check the voltage and thermal ratings of the exact selected part number. 2. Place C1 and C2 on the highlighted footprints. They have no positive and negative ends. 3. Follow the specified solder process. Inspect and clean the board before placing the JFETs. Avoid repeated heating of the film parts. **Check before proceeding:** Trace each capacitor from its input conductor to ground in the net table. **Teaching note:** The source builder damaged film capacitors during teardown. Do not use a generic high-temperature reflow recipe without checking the part. **Retrieval question:** What is the role of C1 and C2 in this reference circuit? **Feedback:** Both capacitors connect from an input leg to ground. They are not in series with the balanced audio conductors. **Blender treatment:** rf-capacitors; isolate C1, C2, R3, R6. Show the placement from above, then rotate for joint inspection. ## Install the dual JFETs — 12 min **Performance objective:** Orient both SOICs and identify the two cascode signal branches. Two packages. Four JFETs. Package orientation is the critical assembly decision in this step. Q1 is the input dual JFET and Q2 is the cascode dual JFET. On the SOIC package, pins 1/2/4 are source/drain/gate for one section; pins 5/6/8 are source/drain/gate for the other. Pins 3 and 7 are substrate connections and float in this source layout. Find the small pin-1 recess, then confirm orientation against the manufacturer’s top-view package drawing. **Demonstration and guided practice:** 1. Use Top view and select Q1. Match the package pin-1 indicator to the PCB pad-1 mark. Repeat independently for Q2. 2. Tack a corner, inspect alignment, then secure the opposite corner and finish the remaining leads. Follow the ordered device’s ESD and thermal handling instructions. 3. Inspect every lead under magnification. Check the source net table for unintended solder bridges; the model’s enlarged dot is an aid, not a substitute for the package datasheet. **Check before proceeding:** Count the transistor sections, then trace Q1 drain 2 to Q2 source 1 and Q1 drain 6 to Q2 source 5. **Teaching note:** The two package bodies do not mean the circuit has only two transistor sections. Do not ground substrate pins simply because a generic SOIC example did. **Retrieval question:** How many JFET transistor sections are inside Q1 and Q2 together? **Feedback:** Each LSK389 contains two matched N-channel JFETs. Two packages provide four transistor sections, arranged in two cascode branches. **Blender treatment:** dual-jfets; isolate Q1, Q2. Show the placement from above, then rotate for joint inspection. ## Wire the XLR connectors — 12 min **Performance objective:** Wire both connectors by contact number while preserving balance. The female input faces the microphone. The male output faces the phantom-powered interface. J2 pads 1, 2 and 3 connect to female XLR contacts 1, 2 and 3. J3 pads 1, 2 and 3 connect to male XLR contacts 1, 2 and 3. Pin 1 is the screen/ground connection; pin 2 is hot; pin 3 is cold. Both signal conductors carry phantom DC at the output. **Demonstration and guided practice:** 1. Identify the moulded contact numbers on each actual connector. Its mating face and solder side are mirror views; never copy left/right positions from a picture. 2. Make the six numbered connections in the Circuit table, keeping the two balanced conductors together and the wires short. Plan insulation and the chassis/screen bond. 3. With everything disconnected, verify each header-to-contact connection by number and check the PCB cannot contact the metal housing accidentally. **Check before proceeding:** Read back all six connections from the actual solder cups to the PCB, rather than relying on wire colours. **Teaching note:** The connector bodies and wire curves are illustrative. Printed contact numbers and the source net table govern the physical wiring. **Retrieval question:** Which wiring rule avoids a mirrored-view mistake? **Feedback:** Number-to-number continuity survives a change of view. Left/right diagrams do not. **Blender treatment:** xlr-wiring; isolate J2, J3, XLR_IN, XLR_OUT. Show the placement from above, then rotate for joint inspection. ## Inspect before first power — 12 min **Performance objective:** Prepare a controlled first-power test without attaching a microphone. Leave the microphone disconnected. Turn the virtual inspection into a real, recorded bench check. Inspect joints and verify the intentional resistive connections first. A protected P48 fixture supplies DC through the normal matched phantom feed resistors. A bare 48 V supply directly across the board is not equivalent. No expected bias-voltage windows have been established for this build. **Demonstration and guided practice:** 1. With power off, compare component orientation, every pad net and connector mapping against Circuit. Check for shorts and debris. Do not expect all pins to be isolated: the resistors create intentional paths. 2. Use a protected/current-limited P48 fixture with no microphone connected and monitors muted. Measure both output legs relative to pin 1; derive each branch current from its measured phantom feed-resistor voltage drop. 3. Check input-to-pin-1 and input differential DC, then check for instability using suitable equipment. Power down if input DC is unexpectedly high, a leg is railed, or behavior is strongly asymmetric. Record the fault rather than guessing a pass. **Check before proceeding:** Record test setup, phantom source voltage, both leg voltages, inferred currents and input DC before a microphone is connected. **Teaching note:** Do not place a current meter directly across XLR pins or a grounded scope clip on a phantom-carrying signal leg. The lesson cannot certify a physical assembly. **Retrieval question:** What should be connected to the microphone input for the first DC check? **Feedback:** Make the first powered DC checks without a microphone. Resolve faults before exposing a microphone or other valued equipment. **Blender treatment:** xlr-wiring; isolate Q1, Q2, J2, J3. Show the placement from above, then rotate for joint inspection. ## Measure gain and close the build — 12 min **Performance objective:** Measure actual gain and document whether the prototype is ready for a mic test. The product specification is a reference. Your build needs its own measurement. Using a suitable DC-safe balanced test setup, measure differential input and output RMS at the same frequency and without clipping. Voltage gain in dB is 20 log10(Vout/Vin). A ratio of 17.78 is 25 dB. That arithmetic does not predict this prototype’s performance. **Demonstration and guided practice:** 1. After the DC and stability checks, apply a small balanced test signal. Measure input and output at 1 kHz with the intended receiving load; calculate gain and record the supply and load conditions. 2. Check response, headroom and level-matched noise. Use an inexpensive dynamic microphone for an initial listening test only after electrical checks, then evaluate the SM7B. 3. Disconnect, discharge and inspect again. Secure and insulate the board in the actual housing, add strain relief as needed, close it, and repeat the relevant checks. **Check before proceeding:** Keep a bench log with readings and conditions. An unanswered or unmeasured item remains open. **Teaching note:** Completing the course records lesson review only. It does not mean the physical circuit passed, or that this build matches factory gain, noise or protection. **Retrieval question:** If Vin is 1 mV RMS and Vout is 10 mV RMS, what is the measured voltage gain? **Feedback:** 20 × log10(10/1) = 20 dB. Use differential RMS measurements at the same frequency, with DC-safe instruments and no clipping. **Blender treatment:** workshop-hero; isolate Q1, Q2, BASE, LID. Show the placement from above, then rotate for joint inspection.